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low skew, 1-to-15, lvcmos/lvttl clock generator 87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 1 g eneral d escription the 87974i is a low skew, low jitter 1-to-15 lvcmos/ lvttl clock generator/zero delay buffer. the device has a fully integrated pll and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. in addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. the clk0 and clk1 pins allow for redundant clocking on the input and dynam- ically switching the pll between two clock sources. guaranteed low jitter and output skew characteristics make the 87974i ideal for those applications demanding well de ned performance and repeatability. f eatures ? fully integrated pll ? fifteen single ended 3.3v lvcmos/lvttl outputs ? two lvcmos/lvttl clock inputs for redundant clock applica- tions ? clk0 and clk1 accepts the following input levels: lvcmos/lvttl ? output frequency range: 8.33mhz to 125mhz ? vco range: 200mhz to 500mhz ? external feedback for ?ero delay clock regeneration ? cycle-to-cycle jitter: ?00ps (typical) ? output skew: 350ps (maximum) ? 3.3v operating supply ? -40? to 85? ambient operating temperature ? available in lead-free rohs-compliant package p in a ssignment 52-lead lqfp 10mm x 10mm x 1.4mm package body y package top view
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 2 b lock d iagram
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 3 0 1 ? ? pll 2 d d d d q q q q 5 5 4 0 1 0 1 clk_sel clk0 clk1 fb_in sel_a pll_sel sel_c fb_sel(0:1) nmr/oe qa0:qa4 qb0:qb4 qc0:qc3 qfb s implified b lock d iagram sel_b fb_0 fb_1 0 0 ? 0 1 ? 1 0 ? 1 1 ?2 sel_c 0 ? 1 ? sel_b 0 ? 1 ? sel_a 0 ? 1 ? vco_sel clk_en
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 4 t able 1. p in d escriptions number name type description 1, 15, 19, 24, 30, 35, 39, 43, 47, 51 gnd power power supply ground. 2 nmr/oe input pullup active high outputs enabled (active). when low, outputs are disabled (high-impedance state) and reset of the device. during reset/output disable the pll feedback loop is open and the internal vco is tied to its lowest frequency. the 87974i requires reset after any loss of pll lock. loss of pll lock may occur when the external feedback path is interrupt- ed. the length of the reset pulse should be greater than one reference clock cycle (clkx) 3 clk_en input pullup synchronizing clock enable. when high, clock outputs qax:qcx are enabled. when low, clock outputs qax:qcx are low. lvcmos / lvttl interface levels. 4 sel_b input pulldown selects divide value for bank b output as described in table 3d. lvcmos / lvttl interface levels. 5 sel_c input pulldown selects divide value for bank c output as described in table 3d. lvcmos / lvttl interface levels. 6 pll_sel input pullup selects between the pll and the reference clock as the input to the di- viders. when high, selects pll. when low, selects the reference clock. lvcmos / lvttl interface levels. 7 sel_a input pulldown selects divide value for bank a output as described in table 3d. lvcmos / lvttl interface levels. 8 clk_sel input pulldown clock select input. when high, selects clk1. when low, selects clk0. lvcmos / lvttl interface levels. 9 clk0 input pulldown reference clock input. lvcmos / lvttl interface levels. 10 clk1 input pullup reference clock input. lvcmos / lvttl interface levels. 11, 27, 42 nc unused no connect. 12 v dd power core supply pin. 13 v dda power analog supply pin. 14, 20 fb_sel0, fb_ sel1 input pulldown selects divide value for bank feedback output as described in table 3e. lvcmos / lvttl interface levels. 16, 18, 21, 23, 25 qa4, qa3, qa2, qa1, qa0 output bank a clock outputs. 7 typical output impedance. lvcmos / lvttl interface levels. 17, 22, 26 v ddoa power output supply pins for bank a clock outputs. 28 v ddofb power output supply pin for qfb clock output. 29 qfb output clock output. lvcmos / lvttl interface levels. 31 fb_in input pullup feedback input to phase detector for generating clocks with ?ero delay? connect to pin 29. lvcmos / lvttl interface levels. 32, 34, 36, 38, 40 qb4, qb3, qb2, qb1, qb0 output bank b clock outputs. 7 typical output impedance. lvcmos / lvttl interface levels. 33, 37, 41 v ddob power output supply pins for bank b clock outputs. 44, 46, 48, 50 qc3, qc2, qc1, qc0 output bank c clock outputs. 7 typical output impedance. lvcmos / lvttl interface levels. 45, 49 v ddoc power output supply pins for bank c clock outputs. 52 vco_sel input pulldown selects vco ?4 when high. selects vco ?2 when low. lvcmos / lvttl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values.
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 5 t able 3a. o utput c ontrol p in f unction t able inputs outputs nmr/oe clk_en qa0:qa4 qb0:qb4 qc0:qc3 qfb 0 x hiz hiz hiz hiz 1 0 low low low enable 1 1 enable enable enable enable t able 3b. o perating m ode f unction t able inputs operating mode pll_sel 0 bypass 1 pll t able 3c. pll i nput f unction t able inputs clk_sel pll input 0 clk0 1 clk1 t able 2. p in c haracteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k c pd power dissipation capacitance (per output); note 1 v dd, v dda , v ddox = 3.465v 15 pf r out output impedance 5 7 12 note 1: v ddox denotes v ddoa , v ddob , v ddoc , v ddofb . t able 3d. s elect p in f unction t able sel_a qax sel_b qbx sel_c qcx 0 20 20 4 1 41 41 6 t able 3e. fb s elect f unction t able t able 3f. vco s elect f unction t able inputs outputs fb_sel1 fb_sel0 qfb 0 0 ?4 1 0 ?6 0 1 ?8 1 1 ?12 inputs vco_sel fvco 0 vco/2 1 vco/4
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 6 t able 4b. lvcmos/lvttl dc c haracteristics , v dd = v dda = v ddo x = 3.3v?%, t a = -40? to 85? t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo x = 3.3v?%, t a = -40? to 85? symbol parameter test conditions minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 2.935 3.3 3.465 v v ddox output supply voltage; note 1 3.135 3.3 3.465 v i dd power supply current 121 ma i dda analog supply current 15 ma i ddox output supply current; note 2 24 ma note 1: v ddox denotes v ddoa , v ddob , v ddoc , v ddofb . note 2: i ddox denotes i ddoa , i ddob , i ddoc , i ddofb symbol parameter test conditions minimum typical maximum units v ih input high voltage sel_a:sel_c, nmr/oe, vco_sel, pll_sel, clk_sel, clk_en, fb_sel0, fb_sel1, fb_in 2v dd v clk0, clk1 2 v dd v v il input low voltage sel_a:sel_c, nmr/oe, vco_sel, pll_sel, clk_sel, clk_en, fb_sel0, fb_sel1, fb_in 0.8 v clk0, clk1 0.8 v i ih input high current fb_sel0, fb_sel1, sel_a:sel_c, clk0, vco_ sel, clk_sel v dd = v in = 3.465v 100 ? clk1, fb_in, nmr/oe, pll_ sel, clk_en v dd = v in = 3.465v 5 a i il input low current fb_sel0, fb_sel1, sel_a:sel_c, clk0, vco_ sel, clk_sel v in = 0v, v dd = 3.465v -5 ? clk1, fb_in, nmr/oe, pll_ sel, clk_en v in = 0v, v dd = 3.465v -100 ? v oh output high voltage; note 1 2.4 v v ol output low voltage; note 1 0.5 v note 1: outputs terminated with 50 to v ddox /2. a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 73.2?/w (0 lfpm) storage temperature, t stg -65? to 150? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 7 t able 5. ac c haracteristics , v dd = v dda = v ddo x = 3.3v?%, t a = -40? to 85? symbol parameter test conditions minimum typical maximum units f max output frequency qx ? 2, vco ? 2 125 mhz qx ? 4, vco ? 2 63 mhz qx ? 6, vco ? 2 42 mhz f vco pll vco lock range; note 5 200 500 mhz t pd sync to feedback propagation delay; note 2, 5 pll_sel = 3.3v, fref = 50mhz -250 100 ps tsk(o) output skew; note 4, 5 measured on rising edge at v ddo /2 350 ps tjit(cc) cycle-to-cycle jitter; note 5, 6 ?00 ps t l pll lock time 10 ms t r / t f output rise/fall time 0.8v to 2.0v 0.15 1.5 ns t pw output pulse width t period /2 - 800 t period /2 ?500 t period /2 + 800 ps t en output enable time 2 10 ns t dis output disable time 2 10 ns all parameters measured at f max unless noted otherwise. note 1: measured from the v dd /2 point of the input to thev ddox /2 of the output. note 2: de ned as the time difference between the input reference clock and the average feedback input signal when the pll is locked and the input reference frequency is stable. note 3: de ned as skew within a bank with equal load conditions. note 4: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddox /2. note 5: this parameter is de ned in accordance with jedec standard 65. note 6: measured as peak-to-peak.
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 8 3.3v o utput l oad ac t est c ircuit o utput s kew o utput r ise /f all t ime c ycle - to -c ycle j itter o utput p ulse w idth /p ulse w idth p eriod sync to f eedback p ropagation d elay p arameter m easurement i nformation
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 9 as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the 87974i provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddox should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. the 10 resistor can also be replaced by a ferrite bead. p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd a pplication i nformation i nputs : clk i nput : for applications not requiring the use of a clock input, it can be left oating. though not required, but for additional protection, a 1k resistor can be tied from the clk input to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvcmos o utput : all unused lvcmos output can be left oating. we recommend that there is no trace attached.
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 10 f igure 2a. 87974i lvcmos/lvttl z ero d elay b uffer s chematic e xample l ayout g uideline the schematic of the 87974i layout example used in this layout guideline is shown in figure 2a. the 87974i recommended pcb board layout for this example is shown in figure 2b. this layout example is used as a general guideline. the layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the p.c. board. q1 3.3v lvcmos driver zo = 50 ohm rs c13 0.01u 3.3v vddo (u1-49) (u1-45) (u1-41) c12 0.1uf c9 0.1uf c10 0.1uf nmr reset pulse or pull up (u1-28) (u1-17) (u1-33) (u1-22) (u1-37) (u1-26) vdd clk_en pll_sel sela selb selc clk_sel ru6 sp rd6 1k ru5 sp rd2 sp rd4 1k ru4 sp rd5 1k ru7 sp rd3 sp ru3 1k rd7 1k ru2 1k c8 0.1uf r7 10 c6 0.1uf c7 0.1uf c16 10u c5 0.1uf c4 0.1uf c11 0.01u sp = space (i.e. not intstalled) c3 0.1uf vdd u3 87974 gnd 1 nmr 2 clk_en 3 selb 4 selc 5 pll_sel 6 sela 7 clk_sel 8 clk0 9 clk1 10 nc 11 vdd 12 vdda 13 fb_sel0 14 gnd 15 qa4 16 vddoa 17 qa3 18 gnd 19 fb_sel1 20 qa2 21 vddoa 22 qa1 23 gnd 24 qa0 25 vddoa 26 gnd 39 qb1 38 vddob 37 qb2 36 gnd 35 qb3 34 vddob 33 qb4 32 fb_in 31 gnd 30 qfb 29 vddofb 28 nc 27 vco_sel 52 gnd 51 qc0 50 vddoc 49 qc1 48 gnd 47 qc2 46 vddoc 45 qc3 44 gnd 43 nc 42 vddob 41 qb0 40 vddo r5 43 zo = 50 receiver r8 43 receiver receiver r1 43 receiver zo = 50 zo = 50 zo = 50 r3 43 clk_sel clk_en selb selc vdd pll_sel sela vco_sel example of reconfigurable logic control input
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 11 f igure 2b. pcb b oard l ayout f or 87974i the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors as close as possible to the pow- er pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc lter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital sys- tems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed rst and should be locked prior to routing other signal traces. ? the differential 50 output traces should have same length. avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the series termination resistors should be located as close to the driver pins as possible.
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 12 r eliability i nformation t ransistor c ount the transistor count for 87974i is: 4225 t able 6. ja vs . a ir f low t able for 52 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 58.0?/w 47.1?/w 42.0?/w multi-layer pcb, jedec standard test boards 42.3?/w 36.4?/w 34.0?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 13 p ackage o utline - y s uffix for 52 l ead lqfp t able 7. p ackage d imensions reference document: jedec publication 95, ms-026 jedec variation all dimensions in millimeters symbol bcc minimum nominal maximum n 52 a -- -- 1.60 a1 0.05 -- 0.15 a2 1.35 1.40 1.45 b 0.22 0.32 0.38 c 0.09 -- 0.20 d 12.00 basic d1 10.00 basic e 12.00 basic e1 10.00 basic e 0.65 basic l 0.45 -- 0.75 0 -- 7 ccc -- -- 0.08
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 14 t able 8. o rdering i nformation part/order number marking package shipping packaging temperature 87974cyilf ics87974cyilf 52 lead ?ead free lqfp tray -40? to +85? 87974CYILFT ics87974cyilf 52 lead ?ead free lqfp tape and reel -40? to +85?
87974i data sheet ?2016 integrated device technology, inc revision e january 26, 2016 15 revision history sheet rev table page description of change date a 10 & 11 added layout guideline and pcb board layout. 4/2/02 a 3 added simpli ed block diagram. 4/4/02 a t7 12 revised package outline drawing. corrected package dimensions table to corre- spond with the package outline drawing. update format throughout datasheet. 11/15/02 b t1 t4a 4 6 pin description table - updated nmr/oe and v ddox pin descriptions. 3v power supply table - changed v dd parameter to ?ore... from ?ositive...? changed i dd max. limit from 105ma max. to 118ma max., and i ddox from 20ma max. to 22ma max. 3/20/03 b t2 t3e 5 5 pin characteristics table - changed c in 8pf max. to 4pf typical. fb select function table - switched fb_selx headings, fb_sel1 heading is in column 1, fb_sel0 heading is in column 2. 5/15/03 b t2 5 12 pin characteristics table - added r out , output impedance row. revised package outline. 7/9/03 c t4a 6 change from die rev. a to b on part marking throughout data sheet. change max. temperature to 70? down from 85? throughout data sheet. power supply dc characteristics table - adjusted: v dda from 3.135v min. to 2.9375v min., i dd from 118ma max. to 125ma max., and i ddox from 22ma max. to 25ma max. 7/23/03 d t4a 6 through out the data sheet the maximum temperature was changed from 70? to 85?. power supply dc characteristics table - i dd changed from 125ma max. to 121ma max. and i ddox changed from 25ma max. to 24ma max. 8/4/03 d 2 & 3 swaped labels for fb_sel0 and fb_sel1 in the block diagram and simpli ed block diagram. 2/9/04 d t3e 5 corrected fb select function table. 6/9/04 d t8 13 ordering information table - added lead-free part number. 10/11/04 d t8 9 14 added recommendations for unused input and output pins. ordering information table - part number and order number is now a revision c. corrected lead-free part number and marking, and added lead-free note. 1/19/06 et8 14 16 updated datasheet? header/footer with idt from ics. removed ics pre x from part/order number column. added contact page. 7/26/10 e t1 4 updated description of nmr/oe pin 04/18/13 e t8 1 14 removed ics from part numbers where needed. features section - removed reference to leaded packages. ordering information - removed quantity from tape and reel. deleted lf note below the table. updated header and footer. 1/26/16
87974i data sheet disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or speci cations described herein at any time, without notice, at idt's sole discretion. performance speci cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the sam e way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of i dt's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expect- ed to signi cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type de nitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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